Formal Equivalence Checking Methodology Engineer
$136,000–$264,500 year
On-site · Santa Clara, California, United States
Job Summary
Develop and maintain robust equivalence checking flows (FEC/FEV) for RTL-to-RTL, RTL-to-Gate, and Gate-to-Gate verification across the VLSI design cycle. Collaborate with ASIC design teams to meet design requirements and constraints; optimize flows for performance, capacity, and debug capabilities; debug verification aborts and constraint issues; provide training and support to IP teams on formal verification methodologies and tools; stay current with advancements in equivalence checking techniques and tools.
Required Qualifications
- BS in Electrical or Computer Engineering or equivalent experience with 3+ years of CAD experience
- MS preferred
- Familiar with Verilog and ASIC design
- Experience with equivalence checking (FEC or FEV) and RTL Linting flows
- Strong scripting skills in Python or Perl
- Excellent problem-solving, debugging, and analytical skills
- Ability to work in a team environment and collaborate with multidisciplinary teams
- Strong communication and documentation skills
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