FE CPIE PI MTS
On-site · Singapore, Singapore
Job Summary
Senior Frontend Central Process Integration Engineer responsible for driving best-in-class product maturity (bits per wafer yield, Repair Density and DPM) at the fastest speed with efficient learning cycles. Requires deep knowledge of FEOL, MOL, CELL, and BEOL processes to identify optimum process integration solutions and to align/standardize methods across DRAM/NAND sites. Collaborates with YE, Device, RDA, and Metrology teams to resolve top yield issues and to enable fast yield ramp with inline visibility, minimizing excursions. Must identify best-known-methods from DRAM/NAND sites and drive cross-network alignment. Travel to Micron sites for face-to-face collaboration. Candidate should have 7+ years in semiconductor process roles and hold a Bachelors/Masters/PhD in EE, Materials Engineering, Materials Science, Physics, or Chemical Engineering. Strong analytical, data-driven decision-making, root-cause analysis, and communication skills are required, along with ability to work across multiple sites and stakeholders.
Required Qualifications
- 7+ years of experience in process related role in semiconductor industry
- Bachelors/Masters/PhD in EE, Materials Engineering, Materials Science, Physics or Chemical Engineering
- Good logical thinking and knowledge in Semiconductor Fabrication process flows
- Understanding of DRAM and NAND operation and structure
- Good model based problem solving and data driven decision making
- Strong presentation skills and ability to communicate with cross-functional teams
- Willingness to travel to Micron sites for collaboration
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