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Renesas Electronics1 week ago

Engineer, Physical Design

On-site · Bengaluru, Karnataka, India

Type
Full Time
Level
Mid Level
Education
Bachelors Degree
Company size
Enterprise
Industry
Semiconductors

Job Summary

Physical Design Engineer to drive block-level/full chip Place & Route and timing closure (Synthesis, PNR, STA and Physical verification). Collaborate with mixed signal custom design teams on full-chip floorplanning to integrate analog macros; perform physical verification (DRC, LVS, Antenna, IR-EM) and debug timing violations; run timing analysis and implement ECOs; handle multi-mode/multi-corner timing closure, RC extraction, cross-talk, and sign-off. Work closely with RTL design to understand design, constraints, and clocking; setup scan insertion and integrate DFT; script in Tcl/Perl to automate workarounds and tool issues; customize flows for finfet technologies. Requires B.Tech or M.Tech in Electronics or Electrical with 2+ years PD experience and at least one taped-out project. Strong Cadence experience, scripting, and collaboration with foundries/IP vendors are expected; deep knowledge of timing libraries, corners, and process variation for 28nm and below. Team-oriented and proactive in learning and improving within a dynamic environment.

Required Qualifications

  • B.Tech or M.Tech in Electronics or Electrical
  • atleast 2+ years experience in physical design & timing closure
  • Owned Physical Design and taped out at least a minimum of 1 projects, at least one of them being a first-generation project
  • Thorough in PD flows, physical verification and multiple tape out experience
  • Worked on Synthesis, timing analysis & closure, generating ECOs
  • Experienced in Cadence synthesis, place and route, timing analysis and verification tools
  • Strong scripting skills - Tcl, perl, csh etc.
  • Ability to create methodologies and automate flows
  • Worked with foundries/IP vendors on tech files, libraries, IP collaterals
  • Very good knowledge of timing libraries, corners/modes, process variations and signal integrity related issues in advanced technology nodes (28nm and below)
  • Ability to work in a dynamic environment with changing requirements
  • Team player with excellent communication skills
  • Highly motivated and inspired to continue learning & improving as an individual and as part of a group
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Renesas Electronics

Engineer, Physical Design

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