Engineer, Physical Design

Physical Design Engineer to execute the full RTL-to-GDS flow for digital and mixed-signal blocks (floorplanning, power planning, placement, routing), perform Static Timing Analysis (STA) and ECOs for timing convergence, analyze Clock Tree Synthesis (CTS) for skew/latency optimization, conduct physical verification (DRC/LVS/Antenna checks), contribute to power optimization (clock gating, power domains, IR drop), and develop/maintain Tcl/Python scripts to automate design tasks. Collaborate with RTL design and Custom Layout teams to ensure clean hand-offs. Requires a Bachelor's degree in Electrical/Computer Engineering (2+ years) or Master’s degree (0-2 years) with strong digital logic, CMOS device physics, ASIC flow knowledge (Synthesis, P&R, STA, Signoff), experience with Cadence Innovus/Encounter and Synopsys ICC2/Fusion Compiler, scripting skills (Tcl/Python/Perl), and Linux/Unix proficiency. Preferred: Advanced process-node coursework, internship/Co-op in Physical Design, familiarity with Mentor Calibre or Synopsys IC Validator, UPF/CPF, timing constraints (SDC), and version control systems (Git/Perforce/Subversion). Salary range: $120,000 - $160,000