Engineer II – Design

Own early-stage backend design tasks for blocks, including DFT RTL hookup, RTL QA checks, SDC creation/review, power estimation and signoff checklist management; perform synthesis and address design issues; implement Design-For-Test (DFT) on complex digital integrated circuits at the block, subsystem or device level (100K to 10M+ gates) coded in VHDL/Verilog; perform physical design flows, Place & Route and close timing on very large and complex ASICs and SOCs in Very-Deep Sub-Micron (VDSM) process technology nodes; potentially work on multiple blocks in parallel; analyze log and report files to ensure the tools are getting the required results and make adjustments to the scripts to get the required results within the scheduled milestones; collaborate with RTL designers, physical design, implementation and DFT teams to ensure early detection and resolution of issues related to RTL, synthesis, constraints, floorplans and timing; communicate regularly with the local project lead to resolve issues and to ensure meeting targeted goals and schedule; document lessons learned, process improvements, and recommendations for future projects; proactively identify opportunities to improve efficiency, parallelize work, and offload engineers; communicate clearly and effectively with global teams (including regular online meetings and written updates).