DV DFT Engineer
HybridTel Aviv, Tel Aviv, Israel or Caesarea, Haifa, Israel
Job Summary
Design Verification Engineer for Cisco SiliconOne DFT team, responsible for establishing and driving DFT verification activities, developing verification plans, environments, checkers, assertions, and coverage models for DFT features; verify DFT architecture in collaboration with DFT, design, architecture, and verification teams; work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features; debug complex pre-silicon issues across RTL, verification environments, and DFT logic; contribute to scalable verification methodologies and best practices, and bridge general DV methodologies with DFT-specific verification needs. The role requires collaboration with cross-functional teams and a strong desire to grow in the DFT DV domain, within a hybrid work model with three days in the office in Tel Aviv or Caesarea.
Required Qualifications
- B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or related field
- 5+ years of experience in design verification roles
- Strong experience with SystemVerilog and UVM-based verification environments
- Experience developing verification plans, coverage models, assertions, and debug flows
- Strong communication skills and ability to work closely with cross-functional teams
- Motivation to learn DFT concepts and become a key contributor in the DFT DV domain
Desired Qualifications
- DFT DV experience
- SystemVerilog
- UVM
- verification environments
- verification plans
- coverage models
- assertions
- debug flows
- SoC verification
- MBIST
- JTAG/IJTAG
- ATPG-related logic
- DFT concepts (scan insertion, memory BIST, boundary scan)
- hybrid work model
- cross-functional collaboration
- strong communication skills
- ability to establish verification activity from the ground up
- high attention to detail
- ownership mindset
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