Director, SoC Design Engineering

Lead end-to-end SoC verification for complex designs by defining scalable, reusable verification methodologies and driving first-pass silicon success. Architect and implement verification strategies across simulation, emulation, and formal methods; develop block-, subsystem-, and SoC-level verification plans with test benches and coverage models; oversee verification closures for interfaces like AXI, ACE, CHI, and interconnects; collaborate with SoC architects, RTL designers, and firmware teams to define verification hooks, assertions, and coverage metrics; manage IP integration (PCIe Gen6/7, DDR5/6, Ethernet) and promote reusable UVM-based flows to boost productivity; lead emulation and performance modeling efforts (Palladium, Veloce) and drive pre-silicon to post-silicon correlation; mentor technical leads and verification engineers and coordinate with post-silicon validation to evolve methodologies and infrastructure.