Director, Design Verification
$195,180–$292,400 year
On-siteSanta Clara, California, United States
Santa Clara, California, United StatesOn-siteFull Time$195,180–$292,400 yearSenior LevelDoctorate Or Professional DegreeLarge
Full TimeSenior LevelDoctorate Or Professional DegreeLarge
Job Summary
Lead DV, emulation, and post silicon validation execution with a zero defect mindset, defining scope, timelines, and methodologies for complex multi-chiplet SOCs. Drive TB architecture implementation, tool evaluation, and continuous productivity improvements while collaborating with Architecture, Design, DFT, and system teams. Hire, build, and retain a high-performance engineering team, addressing training needs and monitoring industry trends. Execute full lifecycle validation from prototype to production ramp-up for CCS product portfolio.
Required Qualifications
- Bachelor's degree in Computer Science, Electrical Engineering or related fields
- 10-15 years of related professional experience
- Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience
- equivalent professional experience in lieu of a formal degree
- 10+ years of experience in design engineering with focus on block level, subs-system level and SOC verification
- Hands on experience with verification methodologies, test-bench development
- Strong experience in coding in scripting languages like Perl, Python, Tcl & UNIX Shell etc
- Strong understanding of ASIC development process
- Proven ability to lead ASIC development teams
- Strong understanding of product development cycle of large SOCs through multiple successful product tape-outs
- Good understanding of SoC architecture, processor cores, memory, and peripheral interfaces
- Excellent communication, interpersonal and presentation skills
- Strong cross-functional leadership skills
- Cross domain knowledge to resolve with design and architecture teams
- Highly motivated, self-driven and curiosity to learn new technologies
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