Digital Verification
$121,000–$121,000 year
On-siteAustin, Texas, United States
Job Summary
Design, develop, and test semiconductor products for the electronic communications industry by defining IP verification plans and writing System Verilog monitors, drivers, and SVA cover properties. Debug failing test cases to identify failure sources, analyze random simulation results for uncovered events, and perform assertion-based formal verification of blocks and IPs. Maintain verification environments including scripts and Make files while ensuring designs meet industry standards and product requirements. Requires a Master's in Electrical and Computer Engineering and expertise in UVM, Verilog, and C/Python.
Required Qualifications
- Master's degree in Electrical and Computer Engineering, Electronics Engineering, foreign equivalent or related field
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 1. Programming Languages C/Python
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 2. Verilog and System Verilog
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 3. Verification skills utilizing UVM (Universal Verification Methodology)
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 4. Computer Architecture
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 5. Digital Design with FGPA
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 6. VLSI System Design
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 7. Verilog RTL debugging utilizing waveforms and source code browsing
- Knowledge gained via completion of a university-level course, internship or related occupation involving: 8. Code and Functional Coverage generation and closure
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