DIGITAL VERIFICATION ENGINEER
$129,846–$129,846 year
On-siteAustin, Texas, United States
Job Summary
Collaborate with architecture and design teams to develop verification plans, functional simulations, and test bench components using UVM. Create and execute test plans for IP, sub-system, or SoC levels while running coverage and regression to analyze gaps and improve simulation models. Debug silicon, develop automation scripts, and refine test cases to enhance coverage reports. Understand development boards and lab equipment to perform digital silicon validation and support successful product releases. Requires a Master's degree in Electrical or Computer Engineering and expertise in Verilog, SystemVerilog, and Python or C/C++.
Required Qualifications
- Master's degree in Electrical Engineering, Electronics Engineering, or Computer Engineering, foreign equivalent or related field
- Computer Architecture
- System-on-a-Chip Design
- Digital Circuit and Logic Design
- UVM Verification and Formal verification
- Testbench
- Physical Design Flow
- Verilog and System Verilog
- Programming language: Python or C/C++
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