Digital Verification Engineer
HybridSanta Clara, California, United States
Job Summary
Design, build, and maintain verification environments for digital subsystems across FPGA and ASIC targets, establishing reusable components like drivers, monitors, and scoreboards. Author directed and constrained-random tests to exercise functional modes and corner cases, driving coverage goals to closure while embedding SVA assertions to catch protocol violations. Run and debug simulations using Modelsim, Questasim, and NC-Verilog, triaging failures to root cause and partnering with RTL designers on fixes. Maintain automated regression suites to ensure rapid feedback and debug efficiently at the waveform level. Support lab bring-up of FPGAs and boards by correlating pre-silicon simulation against real hardware, validating register maps and interfaces with firmware engineers. Contribute to verification exit criteria for design milestones to ensure zero functional escapes before tape-out.
Required Qualifications
- 3–7 years of digital verification experience on FPGA or ASIC designs
- Proficiency in Verilog
- SystemVerilog
- Hands-on experience with logic simulators — Modelsim / Questasim and/or NC-Verilog
- Solid grounding in logic-simulation and verification fundamentals — testbench construction, constrained-random stimulus, functional / code coverage, and assertions
- BS/MS in Electrical Engineering, Computer Engineering, or a related field
Desired Qualifications
- Working knowledge of digital design and architecture (RTL design, pipelines, clock-domain crossing, bus / interconnect protocols)
- Experience collaborating with software / firmware teams on system bring-up and HW/SW co-validation
- Structured verification methodology experience (UVM or equivalent)
- Familiarity with networking / switching datapaths or high-speed interfaces
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