Digital IP Principal Verification Engineer
On-site · Austin, Texas, United States
Job Summary
Digital IP Principal Verification Engineer at NXP in Austin, responsible for defining the verification strategy for an IP or sub-system, executing digital functional verification to ensure adherence to specifications, and authoring verification content (testbenches, stimuli, SVAs, monitors, drivers) while developing and maintaining verification environments and tooling. Includes writing IP verification plans, SystemVerilog stimulus, random and directed test cases, assertion cover properties, formal verification, debugging failing testcases, collecting and analyzing coverage, and leveraging AI to augment production work products. Requires SystemVerilog, UVM, verification experience, and a bachelor’s in an engineering discipline; positioned for senior-level contributors with related experience.
Required Qualifications
- Minimum BSEE/BSCE/BSCS
- MSEE/MSCE/MSCS a plus
- Minimum 6 years of experience in IP or SoC design or verification
- Verilog, SystemVerilog, UVM coding skills required
- Verification skills (test planning, testcase, testbench, simulation, debug) required
- Other programming skills (Python, C/C++, Perl, TCL, etc.) a plus
- Design skills (design documentation, RTL coding, synthesis, static and formal checkers, etc.) a plus
- Knowledge of ARM AMBA protocols a plus
- Ability to work independently and in small teams without close supervision required
- Proficiency in efficient use of AI to augment generation of work products
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