Digital Design Engineer
HybridVancouver, British Columbia, Canada
Job Summary
Design and develop RTL for AMD's PCI Express (PCIe) IP across server, client, GPU, and semi-custom products, defining microarchitectural features and driving high-quality implementation with timing closure and CDC analysis. Collaborate with verification engineers to support simulation, debug, and issue resolution throughout the project lifecycle, then participate in silicon bring-up to address post-silicon and customer-reported problems. Optimize low-power design techniques while maintaining performance targets and support design reviews to improve methodologies. Work within a global team to deliver innovative, power-efficient solutions for next-generation computing, applying strong analytical skills and a commitment to engineering excellence in a hybrid role in Vancouver.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Engineering Science, or a related field
- Extensive experience in ASIC/SoC digital design and RTL development using Verilog/SystemVerilog
- Strong understanding of synchronous digital design principles and multi-clock domain implementations
- Hands-on experience with lint, CDC, and timing analysis methodologies and tools
- Experience creating or contributing to technical specifications and microarchitecture documentation
- Knowledge of low-power design techniques and ASIC design flows
- Familiarity with silicon validation and hardware debug using lab equipment such as logic analyzers and oscilloscopes
- Understanding of high-speed interface protocols such as PCI Express (PCIe), USB, SATA, Ethernet, or similar technologies
- Experience collaborating across architecture, verification, physical design, and silicon validation teams
- Must be able to work in Vancouver, British Columbia, Canada
- Must be available for hybrid work arrangements
Desired Qualifications
- Master's degree preferred
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