DFT Verification Engineer
On-siteTaipei, Taiwan, Taiwan or Hsinchu, Taiwan, Taiwan
Job Summary
Verify custom analog macros by partnering with Design, Integration, and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP, cluster, and full chip levels. Generate test patterns and perform chip bringup while collaborating with the CAD team to optimize and smooth the simulation flow. Requires a Master's degree in Electrical or Computer Engineering with 3+ years of DFT or design experience, strong debugging skills using RTL/Gate-level tracing tools (Verdi) and simulation tools (VCS), and familiarity with SOC architecture. Fluency in English is required. This role supports NVIDIA's mission to validate the world's largest design across consumer graphics, self-driving cars, and artificial intelligence.
Required Qualifications
- Master degree of Electrical Engineering/Computer Engineering/Computer Science
- 3+ years of DFT or design experiences
- Strong debugging and analytical skills with RTL/Gate-level design tracing(Verdi) and verification simulation tool(VCS)
- Familiarity with SOC basic architecture(clock,reset,power rail,IO pad,package)
- Understanding of Design for Testing including Scan/ATPG/BIST/JTAG
- Fluent English communication
Desired Qualifications
- Skills of Python/Perl/Tck/C/C++
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