DFT Implementation Engineer
$141,910–$200,340 year
On-siteAustin, Texas, United States
Job Summary
Develop logic design and RTL coding to support DFT features such as SCAN, MBIST, and BSCAN. Provide timing closure support and test content generation for manufacturing while collaborating on architecture and microarchitecture features for SoCs. Write, integrate, and verify RTL and structural code, drive verification efforts, and develop high-volume manufacturing content for rapid bring-up on automatic test equipment. Optimize designs to meet power, performance, area, and test coverage goals. Collaborate with post-silicon and manufacturing teams to verify features on silicon and document learnings. Work in Shift 1 in Austin, Texas, with a target annual salary of $141,910 to $200,340.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of experience in DFT, SoC design, or related semiconductor design areas
- Tessent Shell flows and SSN methodology
- Hands-on experience with ATPG, scan insertion, and/or MBIST/repair RTL design experience using hardware description languages such as Verilog, VHDL, or SystemVerilog
- Shift 1 (United States of America)
- Primary Location: US, Texas, Austin
- Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance
- Position of Trust N/A
- Work Model for this Role This role will require an on-site presence
Desired Qualifications
- Tessent Fast IO, ISTK, and related methodologies
- Exposure to or interest in large ASIC applications in design or test
- Familiarity with advanced DFT techniques for low-power and high-performance SoC designs
- Understanding of industry standards such as IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), IEEE 1500 (Core Test), and IEEE 1838
- Experience with industry-standard DFT tools such as Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, or Cadence Modus
- Proficiency in scripting languages such as TCL, Perl, or Python for design automation
- Knowledge of timing constraints, UPF, and low-power design and test methodologies
- Experience working across cross-functional teams or contributing to complex SoC projects
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