DFT engineer-(Staff/ Senior Staff)
On-siteSingapore, Singapore or South East, Eastern Region, Republic of Uganda
Job Summary
Conduct scan insertion, boundary scan, MBIST, and ATPG for ultra-low power SoCs using standard EDA tools. Develop and implement low-power DFT architecture while generating structural test vectors to analyze and improve coverage, test time, and test cost. Perform pre/post-layout scan and MBIST simulations and collaborate with designers on STA, physical, power, and logical issues. Work with test engineers to bring up test vectors on silicon, focusing on hierarchical DFT implementation and scan compression strategies. Requires BS/MS in ECE/EE with 7+ years of DFT experience, including RTL and Tcl scripting.
Required Qualifications
- BS/MS in ECE/EE
- at least 7 years of experience in DFT implementation
- Skilled in different types of DFT structures, including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan and MBIST
- Experience in creating and implementing hierarchical DFT architecture in complex SoC
- Experience in Low-Power DFT and MBIST
- Experience in test time and test coverage analysis for scan and MBIST patterns
- Experience in working with test engineering team to bring up production test program
- Extensive knowledge of timing concepts and constraint development
- Experience in developing scan ATPG and MBIST test benches and simulation in pre/post-layout environments
- Experience in RTL
- Strong verbal and written English communication skills
Desired Qualifications
- Experience in scripting like Tcl
- Experience with GLS (gate level simulation)
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