DFT (Design For Test) Engineer
$120,000–$150,000 year
On-site · San Jose, California, United States
Job Summary
The DFT Engineer role focuses on ensuring robust testability for integrated circuits throughout their lifecycle. Key responsibilities include developing DFT architectures, integrating DFT methodologies, collaborating with design teams, analyzing test results, and executing verification plans for DFT features. The ideal candidate should possess over 10 years of experience in DFT engineering, a strong understanding of digital design, proficiency in System Verilog, and be familiar with scripting languages. A Bachelor's degree in a relevant field is required, with a Master's preferred.
Required Qualifications
- 10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.
- Deep understanding of digital design, verification methodologies, and DFT implementation practices.
- Proficiency in System Verilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
- Scripting and automation experience using Python, Perl, or TCL.
- Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments.
- Strong analytical and debugging skills.
- Excellent communication and collaboration abilities.
Desired Qualifications
- Mixed-signal DFT methodologies and integration of analog testability into SoC workflows.
- Industry standards such as IEEE 1149.1 (JTAG), IEEE 1500, and experience applying them in complex designs.
- Yield analysis, product engineering, and contributions to test cost reduction and quality improvement programs.
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