DFT Design Engineer
HybridBengaluru, Karnataka, India
Job Summary
Design, implement, and validate Design-for-Test (DFT) solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs. Develop and validate TAP/JTAG, IJTAG, Boundary Scan, MBIST, and Scan/ATPG methodologies while driving test access, pattern generation, and coverage optimization. Collaborate with Design, Verification, Physical Design, and Manufacturing Test teams to debug scan, at-speed, and silicon bring-up issues, perform root-cause analysis, and lead technical reviews. Execute RTL and Gate-Level Simulation validation, adopt DFT best practices, and implement continuous process improvements. This role supports Intel's product lifecycle and requires strong technical leadership and communication skills.
Required Qualifications
- Bachelor's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field
- Master's Degree in Electrical Engineering, Microelectronics, VLSI or related field
- 10+ years of experience
- 8+ years of experience
- TAP/JTAG
- IJTAG (IEEE 1687)
- Boundary Scan (IEEE 1149.1)
- MBIST
- Scan Compression
- ATPG
- Verilog/System Verilog
- Tcl/Perl/Python scripting
- DFT verification
- silicon debug
- strong communication and technical leadership skills
Desired Qualifications
- Scan Insertion
- DFT features
- RTL design for DFT and verification
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