Design Verification Engineer - SoC
$100,000–$120,000 year
On-site · San Jose, California, United States
Job Summary
The Design Verification Engineer will ensure the custom IPs are robust, high-performance, and silicon-ready, collaborating with architects, RTL designers, and software developers to validate correctness and performance across the hardware-software stack. Key responsibilities include verifying performance features, identifying performance bottlenecks, developing test plans, and improving architectural performance models. Candidates should have experience in ASIC/SoC design and verification, expertise in SystemVerilog and Python, and knowledge in architecture and performance modeling.
Required Qualifications
- ASIC/SoC Design & Verification Experience
- Strong understanding of digital design, RTL, and ASIC design flows.
- Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.
Desired Qualifications
- Hands-on experience with performance verification, simulation, and modeling.
- Skilled in writing Python scripts for automation, data analysis, and performance modeling.
- Experience building and maintaining performance models for chip subsystems.
- Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning.
- Some exposure to kernel level performance metrics and profiling tools.
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.