Design Verification Engineer- Senior Associate- Technology
On-siteBucharest, București, Romania or Cluj-Napoca, Cluj County, Romania
Job Summary
Conduct full front-end chip verification from verification plans to coverage closure, developing next-generation core technology products for customers. Lead and mentor younger verification engineers on the team while utilizing System Verilog and UVM to drive regression and coverage analysis. Manage verification environments and modules to closure, leveraging third-party VIPs and interconnects. Requires SOC level experience, Git/Perforce proficiency, and JIRA usage. Full front-end chip verification from verification plans to coverage closure, developing next-generation core technology products for customers. Lead and mentor younger verification engineers on the team while utilizing System Verilog and UVM to drive regression and coverage analysis. Manage verification environments and modules to closure, leveraging third-party VIPs and interconnects. Requires SOC level experience, Git/Perforce proficiency, and JIRA usage.
Required Qualifications
- Good working knowledge of System Verilog and UVM
- Working knowledge of regression and coverage analysis tools
- Has developed an environment and taken a module to verification closure OR has significantly altered an existing environment and taken a module to verification closure
- Working experience with modern revision control systems: Git, Perforce, SVN
- Working experience with JIRA or similar ticketing systems
Desired Qualifications
- Experience with interconnects and memory controllers
- Experience with third party VIPs in their verification environment
- SOC level experience
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