Design Verification Engineer
On-siteMenlo Park, California, United States
Menlo Park, California, United StatesOn-siteContract
Contract
Job Summary
Conduct design verification for digital systems using SystemVerilog, UVM, and Verdi/VCS to debug simulation failures and guide design. Develop test plans with coverage and constrained-random analysis, leveraging Python3, Bash, and Tcl scripting. Apply expertise in fixed-point and floating-point arithmetic while documenting results and characterizing performance. Requires 3+ years of UVM experience and 5 years of industry background; full tape-out experience preferred. Located in Menlo Park, CA.
Required Qualifications
- BSEE/MSEE/BSCompE/MSCompE with 5 years of industry experience
- 3+ years of UVM experience
- Deep understanding of coverage, constrained-random, transaction level
- Experience with Verdi/VCS
- Experience with test plan documentation
- Familiarity with Python3/Bash/Tcl scripting
- Experience with debugging simulation failures to guide digital design
- Experience with fixed-point arithmetic
Desired Qualifications
- BSEE/MSEE/BSCompE/MSCompE with 10 years of industry experience
- Experience with performance analysis and performance characterization
- Experience with using a Hierarchical Verification Plan
- Experienced with a full ASIC/SOC tape out from beginning to end
- Experience with video processing or graphics pipelines
- Experience with floating-point arithmetic in addition to fixed-point arithmetic
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