Design Verification Engineer - Internal IP
$120,000–$240,000 year
On-site · San Jose, California, United States
San Jose, California, United StatesOn-siteFull Time$120,000–$240,000 yearMid LevelNot SpecifiedStartup
Type
Full Time
Level
Mid Level
Education
Not Specified
Company size
Startup
Job Summary
Join our Internal IP DV team as a Design Verification Engineer to validate custom IPs for performance and robustness. Responsibilities include developing UVM/SystemVerilog testbenches, defining and executing verification plans, debugging complex issues, and collaborating with cross-functional teams on functionality and design intent. Ideal candidates will have proficiency with UVM, strong debugging skills, and practical experience in digital design verification.
Required Qualifications
- Proficiency with UVM and SystemVerilog.
- Strong debugging and problem-solving skills for complex digital designs.
- Solid knowledge of computer architecture and digital design fundamentals.
- Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
Desired Qualifications
- Familiarity with SystemVerilog Assertions (SVA) and formal verification techniques.
- Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
- Scripting skills (Python/Perl/TCL or similar) for automation, debug and regression flows.
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.