Design Verification Engineer Intern - Fall 2026

Design Verification Engineer Intern for Fall 2026 at Marvell. You will verify the circuitry inside our chips for general market and customer-specific use, ensuring designs meet specifications for high-speed data transfers. Responsibilities include collaborating with architects, designers, and verification teams to verify functional blocks and subsystems, verifying block requirements for area, power, performance, and latency; assisting with full-chip verification; debugging with design and physical design engineers to fix timing issues; and writing clear documentation describing verification approaches. Candidates should demonstrate teamwork and independent initiative, strong problem-solving and communication skills, and some exposure to Verilog/SystemVerilog or other HDLs, digital logic, and computer architecture. On-site, full-time internship with competitive CAD-based compensation in CAD per hour. Must be enrolled in a university program pursuing BS/MS in relevant engineering fields; knowledge of semiconductor ASIC verification methods and Ethernet/cryptographic technologies is a plus. The role involves cross-functional collaboration with engineers across disciplines and a focus on learning and contributing to advanced semiconductor verification projects.