Design Verification Engineer - Interface IP
$180,000–$240,000 year
On-site · San Jose, California, United States
Job Summary
The Design Verification Engineer will take ownership of one or more IP subsystems such as PCIe, Ethernet, and CPU, ensuring architecture requirements are met. Responsibilities include developing and maintaining UVM/SystemVerilog-based verification environments, validating interaction of external IPs, and driving coverage closure for comprehensive verification. Successful candidates will thrive in fast-paced environments and possess strong verification methodologies knowledge, with a preference for those who can handle vendor IP configurations.
Required Qualifications
- 5+ years of design verification experience
- Hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM
- Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
- Collaborate with cross-functional teams and communicate technical insights
Desired Qualifications
- Experience handling vendors and integration of IP/VIP’s
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