Design Verification Engineer

Design Verification Engineer responsible for developing verification strategies, tests, and coverage for Cerebras' wafer-scale AI chip designs. Work with architects, designers, post-silicon, and software engineers to ensure silicon-quality designs; create reusable verification environments with stimulus, checkers, assertions, and coverage; implement tests, manage regressions, gather coverage, and debug failures; collaborate across RTL design, physical design, firmware, and validation; analyze complex issues across simulation, emulation, and silicon bring-up; contribute to verification methodology and infrastructure improvements. Required: advanced debugging, SystemVerilog testbench (DPI, UVM), strong software engineering practices, scalable testbenches, experience with simulators and waveform viewers, Python or Perl scripting, and 3+ years of verification experience; BS/MS in CS or EE preferred. Remote candidates welcome; base salary range $120k–$240k.