Design Verification Engineer
$143,800–$230,000 year
On-siteSan Jose, California, United States
Job Summary
Design Verification Engineer at Broadcom leading subsystem verification in ASIC/SoC development. Responsibilities include creating verification environments with SystemVerilog and UVM, designing verification components (UVM agents and behavioral models), implementing coverage and assertions, and developing random and directed test cases. Will analyze and debug simulation results and coverage, and collaborate with design and verification teams to resolve verification trade-offs. Requires a Bachelor’s degree in a related field, 12+ years of experience in verification, and strong SystemVerilog, UVM/OVM, C/C++, Perl, and scripting skills. Must be legally authorized to work in the US. Location: San Jose, CA (on-site).
Required Qualifications
- Bachelor’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent
- 12+ years relevant industry work experience
- Experience verifying designs at system level and block level
- Fluent knowledge of RTL verification methodologies including SystemVerilog
- Strong experience in ASIC design verification flows and DV methodologies
- Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting
- Strong and independent design debugging capability
- Must have legal authorization to work in the US
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