Design Verification and Emulation Manager

Lead and scale Efficient’s verification and emulation organization for ASIC/SoC products, owning end-to-end verification strategy from block-level to full-chip, driving emulation-based validation for early software enablement, and building a high-performing team of verification and emulation engineers. Own UVM-based methodology (constrained-random, coverage-driven closure, assertions, formal verification), drive emulation platform strategy and hybrid simulation-emulation methodologies, enable system-level validation on emulation, deliver pre-silicon platforms for early software development, manage dashboards and risk, and collaborate with RTL design, architecture, DFT, physical design, and post-silicon teams to support tapeout readiness and volume production.