Design For Test Engineer III (IC)
$95,900–$170,500 year
On-siteSan Jose, California, United States
Job Summary
Implement DFT implementation for 3nm and 5nm Networking chips, including RTL checks for scan-insertion compatibility using Synopsys Spyglass and Tessent TestKompress. Generate compressed and uncompressed ATPG patterns with Mentor Tessent, Cadence Modus, and Synopsys Tetramax, while performing pattern simulation with and without timing across various corners. Debug mismatches using Verdi and enhance the DAeRT DFT flow with scripting in Perl, Shell, and TCL. Manage MBIST insertion and verification on blocks and top silicon, ensuring IEEE 1149.1 JTAG insertion and verification for multi-million gate count SoCs in networking and consumer verticals.
Required Qualifications
- 5 – 7 Years of experience in DFT Scan-Insertion
- ATPG
- GLS
- Pattern Simulations (with and w/o timing)
- MBIST Insertion and Verification
- Experience in IEEE 1149.1 JTAG Insertion and verification
- Scripting languages like Perl, Shell, TCL
- Worked on multi-million gate count SoCs
- area of Networking
- Consumer
- various IPs like PLL, Serdes
- B. Tech
- M.Tech in Microelectronics/Electronics
- Excellent communicator
- Low power DFT
- Must be able to travel to an Arrow Client office location as requested by Arrow Client leadership
Desired Qualifications
- DFT implementation for 3nm and 5nm Networking chips
- IP DFT work
- RTL checks for scan-insertion compatibility
- using Synopsys Spyglass Scan-Insertion
- using Tessent TestKompress
- ATPG pattern generation: Compressed and Uncompressed Mode
- Tools: Mentor Tessent
- Cadence Modus & Synopsys Tetramax
- Pattern Simulation: Without timing, With timing for different corners
- Tools: VCS
- Mismatch debug using Verdi
- Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation
- in project Makefile enhancement using extended scripts and targets for flow enhancement
- MBIST Insertion and Verification done on block on top Silicon
- debug and bring-up done for block and top
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