Design for Test (DFT)

Design for Test (DFT) Engineer to implement, validate, and optimize DFT methodologies across complex SoC designs, including Scan insertion, ATPG generation, MBIST, LBIST, and Boundary Scan at RTL and gate levels. Collaborate with design, verification, synthesis, STA, and validation teams to develop robust DFT architectures ensuring high test coverage and manufacturability; generate/validate ATPG patterns through simulation and coverage analysis; validate DFT implementations across RTL and gate levels; debug DFT issues and contribute to automation, tooling, and process improvements. Proficient with Verilog/VHDL and scripting/programming (TCL, Perl, Python, C/C++); experience with Synthesis, STA, LEC, verification, and physical design teams; strong problem-solving and cross-functional collaboration skills; familiar with industry-standard EDA tools from Siemens, Synopsys, and Cadence. A detail-oriented engineer focused on delivering high-quality, testable silicon solutions.