Design Engineer III
On-site · Austin, Texas, United States or Sunnyvale, California, United States
Job Summary
Perform comprehensive power analysis from RTL to GDSII, contribute to development, improvement, and automation of power analysis flows, and analyze large datasets for power modeling. Investigate and address power inefficiencies, providing actionable feedback to the RTL design team. Leverage RTL-to-GDSII design flow in 7nm and below nodes, with low-power implementation (power gating, multiple rails, UPF), and tools such as PrimeTime PX/PrimePower and Power-Artist. Require scripting with Python and ML/AI frameworks, solid RTL design principles, and experience in RTL power optimization. Preferred experience includes synthesis and Place and Route (PnR) flows, IP power analysis, and building run-time estimation models for software/firmware teams.
Required Qualifications
- Demonstrated experience with RTL-to-GDSII design flow usage and development in advanced technology nodes (7nm and below)
- Expertise in low-power implementation and signoff, including power gating, multiple voltage rails, and UPF usage
- Proven experience in power analysis and reduction utilizing industry-standard tools such as PrimeTime PX/PrimePower
- Proficiency in scripting languages, with a strong emphasis on Python and ML/AI frameworks
- Working knowledge of RTL design principles
- Experience in RTL power optimization using specialized tools like Power-Artist
- Ability to learn quickly, explore new ideas, and iterate rapidly to achieve optimal results
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