Design Engineer II
On-siteHyderabad, Telangana, India
Job Summary
Develop TFM to optimize PPA for IP's and Soft Controllers, managing regression infrastructure that tracks RTL/flow development quality. Conduct physical design implementation using Cadence EDA tools including Genus, Innovus, and Conformal while developing automation scripts with AI to reduce design execution turnaround time. Perform PPA characterization and flow optimization for performance-oriented and power-oriented best-in-class IP cores across advanced process nodes on TSMC, Intel, Samsung, and Rapidus Foundries. Requires MS/MTech/BE/BTech in Electronics with 2+ years experience and hands-on knowledge of complete ASIC Design Flow.
Required Qualifications
- MS/MTech/BE/ BTech in Electronics from reputed institutes
- 2 + years' experience
- Physical design experience in ASIC design environment
- Knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing, Timing Analysis, Power Analysis and Formal Verification
- Prior experience in Logic Synthesis and PPA optimization techniques
- Logic Equivalence Checks ( LEC ) debug experience for production designs
- Detailed understanding of synthesis flows
- Hands on experience in developing, debugging synthesis flows with EDA tools such as Genus, Fusion Compiler
- Excellent leadership, communication, analytical and problem solving skills
- Solid scripting skills including Python and Tcl
- Self-motivated
- Good team player
Desired Qualifications
- Experience with TSMC, Intel, Samsung and Rapidus Foundries
- Experience developing TFM to optimize PPA for IP's
- Soft Controllers PPA characterization and optimization of flow for performance-oriented and power-oriented best-in-class IP cores in advanced process nodes
- Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs
- Experience with backend tools - Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus
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