Design Engineer
$120,000–$192,000 year
On-site · San Jose, California, United States
Job Summary
Utilize physical design expertise for implementation of complex designs in advanced technology nodes (2nm/3nm/5nm). Responsibilities include netlist-to-GDS implementation, floorplanning, place and route, STA, and physical verification (LVS/DRC/ANT/ERC). Engage with designers, write TCL scripts for custom placements and routing, and perform timing analysis and clock tree synthesis. Compensation includes a competitive salary, discretionary annual bonus, equity opportunities, and comprehensive benefits.
Required Qualifications
- MSEE/MSCS with 6+ years of experience or BSEE/BSCS with 8+ years of experience
- Expertise in Cadence Innovus/Atop physical design tools
- Experience with Calibre LVS/DRC
- Strong TCL/Python scripting knowledge; Perl knowledge is a plus
- Good debug skill and be able to work around issues
- Tape out experience
- Ability to work closely with RTL & DFT designers
Desired Qualifications
- Hands on experience with hierarchical top level floorplanning
- Experience with IO ring design
- Experience with place and route
- Knowledge of clock tree building
- Experience with STA
Additional Requirements
- Qualified applicants will be considered without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status, or any other characteristic protected by federal, state, or local law.
- Qualified applicants with arrest and conviction records will be considered consistent with local law.
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