Defect Reduction Engineer
$76,000–$120,000 year
On-siteAustin, Texas, United States
Job Summary
Conduct deep-dive correlation analyses of tool trend data to identify underperforming equipment and trace defects to their root cause for rapid mitigation. Define inline inspection methodologies and establish robust monitoring plans during New Product Introduction (NPI) for advanced nodes ranging from 14nm to legacy processes. Collaborate with Yield Enhancement, Process Integration, and Unit Process teams to establish Best Known Methods and reduce Same Wafer, Last Year defectivity. Serve as the primary technical liaison for foundry customers and support technology transfer from Samsung HQ in South Korea. Manage Failed Chip Count plans and weekly module meetings to ensure yield targets are achieved across diverse technology nodes.
Required Qualifications
- Bachelor's degree in Electrical, Chemical, Mechanical Engineering, Material Science, Chemistry, Physics, or a related technical field
- Minimum of 5 years of proven experience in semiconductor process engineering
- Specialization in defect monitoring, reduction, process integration, or yield engineering
- Strong preference for candidates with a track record in leading-edge logic technology development (14nm or below)
- Deep understanding of semiconductor manufacturing equipment (e.g., Lithography, Etch, CMP)
- Proficiency in advanced defect inspection and review tools (e.g., Bright Field, Dark Field, E-beam, Vis-edge)
- Expert-level application of SPC and DOE methodologies
- Proficiency in Klarity Defect or similar advanced analytical platforms
- Strong data mining and troubleshooting capabilities
- Demonstrated project management success in driving solutions for complex technical problems from identification to closure
- Ability to manage multiple high-priority tasks in a fast-paced environment with minimal supervision
- Excellent communication and presentation skills
- Proven ability to influence cross-functional teams (YE, PIE, UP)
- Self-starter mindset
- Commitment to meeting strict deadlines and production schedules
- Authorization to access information subject to U.S. export control laws or eligibility for government authorization
Desired Qualifications
- Experience in New Product Introduction (NPI)
- Experience with Global Process Management (GPM) setup
- Experience with specification audits
- Experience with tool spread analysis
- Experience with Non-Product Wafer (NPW) defectivity
- Experience with Same Wafer, Last Year (SWLY) defectivity
- Experience with Failed Chip Count (FCC) and trend monitoring plans
- Experience with legacy production technology nodes (45nm, 32nm, 28nm)
- Experience with foundry processes
- Experience with Yield Enhancement (YE)
- Experience with Process Integration (PIE)
- Experience with Unit Process (UP) engineering
- Experience with Best Known Methods (BKMs)
- Experience with inline inspection methodologies
- Experience with root cause analysis
- Experience with process excursions
- Experience with cross-functional collaboration
- Experience with technical liaison roles for foundry customers
- Experience with technology transfer from Samsung HQ in South Korea
- Experience with weekly module meetings
- Experience with yield and performance targets
- Experience with chronic and ad-hoc yield killers
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