Debug Validation Engineer — Multiple Levels
On-siteBristol, England, United Kingdom
Job Summary
Lead post-silicon debugging and validation efforts for AI compute silicon and platform technologies by analyzing intricate silicon, firmware, software, and system-level problems during bring-up and characterization. Drive debug of CPU, memory, interconnect, and high-speed I/O subsystems under functional, stress, and workload conditions while developing structured methodologies and automated infrastructure using Python. Analyze logs, traces, and telemetry to isolate failures, support silicon readiness reviews, and communicate technical risks to engineering leadership. Operate autonomously across hardware, firmware, and software teams to advance product quality and release decisions within Graphcore's SoftBank-backed AI ecosystem.
Required Qualifications
- Strong experience in bare metal environments
- Strong understanding of SoC and platform architectures
- Expertise in debug infrastructure and post-silicon debug methodologies
- Strong programming skills in Python, C, or debug scripting languages such as CMM or equivalent experience
- Highly motivated self-starter with a collaborative and team-oriented approach
- Ability to collaborate across teams and programming languages to uncover root causes of deep and complex issues
- Experience of the post-silicon validation process applied in digital ASIC environments
- Strong Linux and Python experience
- Outstanding communication skills and the ability to collaborate effectively to solve complex problems
- Excellent problem-solving, analytical, and diagnostic skills
- Deep knowledge of scan, DFT, JTAG, and trace infrastructure
- Strong debug skills including fault tree analysis, failure isolation, fishbone methodologies, and system-level debug techniques
- Capability to operate autonomously on technically intricate debug and validation tasks spanning hardware, firmware, and software areas
Desired Qualifications
- Understanding of DFT flows from insertion through post-silicon validation
- Experience developing tooling for parsing and analyzing debug data, including scan dump parsing
- Driver-level experience with one or more of the following technologies: PCIe, Ethernet, Memory technologies including LPDDR, DDR, and HBM, Peripheral interfaces such as I2C, I3C, and SPI
- Experience using CoreSight and similar debug infrastructure including CTI, ETx, DStream, JLink, Lauterbach, ATB, and STM or equivalent experience
- Strong understanding of mixed-signal components like PLLs, high-speed PHYs, and IC control/communication protocols
- Experience with Arm CPU architectures, system IP, and associated debug tooling
- Experience with AMBA protocols
- Understanding of ML applications and associated workloads
- Experience in characterization, failure analysis, test development, statistical analysis, and customer support
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