Debug/Trace/Profiling Design Engineer
On-site · Boston, Massachusetts, United States or Austin, Texas, United States
Job Summary
SiFive is seeking a hardware design engineer to architect, design and implement debug, trace and profiling hardware for RISC-V IP across scalable processor cores. The role involves building highly configurable hardware generators, leveraging Chisel/FIRRTL, and integrating into the SiFive IP portfolio (Essential, Intelligence, Performance, Automotive). Responsibilities include leading enhancement of debug/trace/profiling capabilities, collaborating with architecture, performance, software and hardware teams, and engaging with customers, partners and tools vendors to shape the future of debugging solutions. Candidates should have 7+ years of architecture/RTL experience in debug/trace/profiling for high-performance processors, extensive RTL design knowledge (Verilog/SystemVerilog/VHDL), proficiency in one programming language (notably Scala/Chisel), and an MS or PhD in EE/CE/CS or related fields. The position requires working in a fast-paced environment, contributing to documentation and verification efforts, and meeting export-control/work authorization requirements for France.
Required Qualifications
- MS/PhD in EE, CE, CS or related technical discipline
- 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high-performance processors
- Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL
- Knowledgeable in debug, trace and profiling architecture and concepts
- Knowledgeable in debug interfaces, JTAG, cJTAG
- Knowledgeable in CPU architectures, power management and SoC design
- Experience in debugging tools, profiling methods
- Knowledge of at least one object-oriented and/or functional programming language
- Knowledge of one or more of: Chisel/Scala, RISC-V architecture, Git/Jira/Confluence
- MS/PhD in EE, CE, CS or a related technical discipline
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