Copy of Principal Mixed Signal RTL Design Engineer
HybridSan Jose, California, United States
Job Summary
Lead micro-architecture and RTL design for Mixed-Signal chiplets focused on intelligent power optimization for AI and HPC. Architect and implement digital PID/cascade control loops for high-frequency multi-phase IVRs, translating validated MATLAB/Simulink models into production-quality Verilog/SystemVerilog. Design supporting digital blocks including ADC interfaces and DPWM modulators, collaborating closely with analog designers on loop compensation and delay budgeting. Analyze and optimize for area, power, timing, and metastability across PVT corners, then support silicon bring-up and controller debugging on lab hardware. Requires BSEE/MSEE/PhD with 8+ years in power management ICs and proficiency in Synopsys/Cadence flows.
Required Qualifications
- Strong mixed-signal background: Solid understanding of power circuits and digital control systems, digital filters etc.
- Proven experience converting control algorithms into clean, synthesizable RTL (HDL Coder or hand-coded Verilog/SystemVerilog)
- Deep knowledge of digital PID implementation challenges: quantization, sampling effects, computational delay, fixed-point arithmetic, and limit cycling
- Familiarity with high-frequency power converter control and digital PWM modulators (DPWM)
- Experience with mixed-signal verification flows (analog-digital co-simulation)
- Good understanding of analog effects impacting digital control: loop delay, sensor non-idealities, inductor non-linearities, PDN resonances
- Proficiency in digital design tools: Synopsys VCS, Verdi, Design Compiler, PrimeTime (or equivalent Cadence flow)
- BSEE / MSEE or PhD with 8+ years of relevant experience in power management ICs or high-performance mixed-signal design
Desired Qualifications
- Prior experience designing digital controllers for integrated voltage regulators (IVRs), point-of-load (PoL) converters, or high-current AI/HPC power delivery
- Experience with formal verification or assertion-based mixed-signal verification
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