Clocking Architect
$187,000–$270,700 year
Hybrid · San Jose, California, United States
Job Summary
Clocking ArchitectRole leads the definition, design, and integration of clocking architectures for Altera’s FPGA/SoC devices, owning end-to-end clocking strategy from subsystem planning to full-chip integration. Responsibilities include delivering clocking specifications and diagrams, coordinating with RTL, physical design, timing, and verification teams, and defining protocol clocking for PCIe, DDR/HBM, ARM, Ethernet, and SerDes. The role covers ML/AI accelerator clocking, DVFS-enabled multi-frequency clock domains, CDC planning and verification, SDC constraint authoring, and DFT clocking methodologies. The candidate will lead OCC strategies, clocking sign-off criteria, and cross-functional reviews, while mentoring junior/senior engineers. The position requires extensive experience with high-speed clocking across PCIe Gen4/5/6, DDR5/LPDDR5/HBM, ARM CoreLink/CMN, and Ethernet up to 400G, plus familiarity with CDC verification tools, constraint protocols, and low-power design (UPF/CPF). A hybrid-remote work model is offered in the Bay Area (San Jose, CA). The role emphasizes collaboration with IP vendors and architecture planning, and involves shaping clock domains for AI/ML workloads and multi-die clocking architectures. Salary range for Bay Area CA: $187,000 - $270,700. Qualifications include a 12+ year track record and a BS/MS in a related field. Eligible applicants must be able to obtain required U.S. export authorizations.
Required Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical field
- 12+ years of industry experience in physical design, SoC/FPGA design, or clocking architecture with silicon tape-outs at 7nm or below
- Proven ownership of full-chip and subsystem-level clocking architecture on high-complexity SoC or FPGA devices
- Deep expertise across PCIe (Gen4/5/6)
- DDR5/LPDDR5/HBM (HBM2E/HBM3) clocking
- ARM CoreLink/CMN interconnect clocking
- Ethernet clocking (1G–400G)
- Configuration interfaces (eSPI, SPI, JTAG, LPC) clock domains
- SerDes clocking for PCIe, Ethernet, high-speed I/O
- Experience architecting clocking for ML/AI accelerator silicon (multi-frequency planes, DVFS, HBM/LPDDR5X integration)
- CDC architecture ownership (full-chip planning, synchronizer strategies, metastability, sign-off)
- SDC constraint authoring and validation using PrimeTime/Cadence Tempus
- DFT clocking (scan, ATPG, OCC, MBIST, LBIST) and associated SDC methodology
- UPF/CPF low-power design methodologies and interaction with clocking
- Scripting in Tcl and/or Python for constraint automation and CDC analysis
- Familiarity with Intel/Altera FPGA architectures a significant advantage
- Experience with clocking for hard IP subsystems within FPGA SoC (e.g., HPS, PCIe hard blocks, memory controllers)
- Background in AI/ML FPGA overlay design and latency optimization through clocking architecture
- Formal CDC verification and model checking (VC Formal)
- Knowledge of IEEE 1500, P1687 (IJTAG) and their clocking implications for embedded DFT instrumentation
- Multi-die/ chiplet clocking architectures (UCIe, BoW, AIB) and die-to-die CDC management
- Tcl/Python constraint automation and analysis tooling
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