Associate Staff Design Verification Engineer

Associate Staff Design Verification Engineer responsible for developing and executing verification plans for SoC/IP blocks and mixed-signal designs, building and maintaining SystemVerilog/UVM-based testbenches, creating directed and constrained-random test cases, driving functional coverage closure, assertions, and regression analysis, debugging RTL and verification failures across simulation and emulation environments, collaborating with RTL designers, architecture, firmware/software, and validation teams, and mentoring junior engineers while contributing to verification strategy and automation/CI flows. The role supports pre-silicon and occasionally post-silicon debug activities and is based in Singapore with a hybrid work arrangement.