Associate Staff Design Verification Engineer
On-site · Singapore, Singapore
Job Summary
Associate Staff Design Verification Engineer responsible for developing verification plans for SoC/IP blocks and mixed-signal designs, building and maintaining SystemVerilog/UVM-based testbenches, creating directed and constrained-random test cases, driving functional coverage closure, debugging RTL and verification failures across simulation and emulation, collaborating with RTL, architecture, firmware/software, and validation teams, improving verification methodologies and automation, and mentoring junior engineers in verification strategy and pre-/post-silicon debug activities.
Required Qualifications
- BS/MS in Electrical or Computer Engineering
- 5–10+ years of verification experience
- Experience with SystemVerilog UVM/OVM
- RTL and GLS simulation/debug
- AMBA/AXI/APB protocols
- Python/Perl/TCL scripting
- SoC/IP verification
- Low-power verification concepts
- CDC/RDC verification
- Mixed signal / AMS verification
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