ASIC/SOC DFT Engineer (Silicon Engineering)
$135,000–$175,000 year
On-sitePalo Alto, California, United States
Job Summary
Evaluate design readiness for scan insertion through RTL and physical design DRC tools. Integrate and verify Design for Test fabrics and IP within subsystems. Run and refine scan insertion recipes via synthesis tools to maximize coverage. Execute ATPG analysis to ensure quality scan chain construction and run gate-level simulations for debugging and post-silicon validation. Collaborate with circuit physical design, ATPG, and manufacturing teams to facilitate high-quality scan coverage in silicon. This role supports SpaceX's Starlink satellite constellation by developing next-generation ASICs for global connectivity infrastructure.
Required Qualifications
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 1+ years of professional experience working with ASICs
- Experience in scan insertion or DFT setup
- Must be willing to work extended hours and weekends as needed
- Must be a U.S. citizen or national, U.S. lawful permanent resident, Refugee, or Asylee (or eligible for required authorizations)
Desired Qualifications
- Understanding of ASIC design flow, methodologies, physical design, and verification
- Experience with high reliability design and implementations
- Good scripting skills (csh/bash, Perl, Python etc.)
- Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
- Familiar with UPF (unified power format), formal verification, and DRC rule checking experience
- Ability to work in a dynamic environment with changing needs and requirements
- Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis
- Enjoys being challenged and learning new skills
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