ASIC Physical Design Technical Leader
$142,000–$181,600 year
On-siteVancouver, British Columbia, Canada
Job Summary
Conduct fullchip floorplan activities by analyzing design architecture, foundry guidelines, and IP constraints to optimize performance, power, and die size. Execute RTL-to-GDSII implementation flows including partition, pin assignment, clock planning, and place-and-route, while performing static timing analysis, power integrity checks, and physical verification. Collaborate with system, package, and EDA vendor teams to define signoff methodologies, identify tool flow efficiency gaps, and implement enhancements. Validate design approaches with Post-Silicon Validation teams and leverage AI tools to improve productivity. Requires 8+ years of physical design experience in 7nm/5nm/3nm processes and proficiency with Innovus, Calibre, and Tempus.
Required Qualifications
- Bachelor's Degree in Electrical Engineering
- 8+ years of Physical Design experience
- Master's Degree in Electrical Engineering
- 6+ years of Physical Design experience
- PhD in Electrical Engineering
- 3+ years of Physical Design experience
- Experience working on Fullchip activities
- Experience with RTL2GDSII flow
- Experience with design tapeouts in 7nm/5nm/3nm or below process technologies
- Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus
Desired Qualifications
- Experience with hierarchical design
- Experience with timing closure
- Experience with physical design convergence
- Experience with power integrity analysis
- Experience with static timing analysis
- Experience defining timing constraints and exceptions
- Experience defining corners/voltage definitions
- Experience in Fullchip floor-planning
- Experience with power grid planning
- Experience with custom clock (H-Tree or Mesh) at chip level
- Experience with Python
- Experience using AI tools by giving accurate prompts
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.