ASIC Physical Design Engineer
On-siteBengaluru, Karnataka, India
Job Summary
Own RTL-to-GDSII execution on complex designs, driving PPA and quality-of-results metrics to closure with minimal supervision. Lead methodology discussions with stakeholders and work with cross-functional partners to align on implementation strategy and schedules. Champion new tools and techniques, devising creative solutions to tough challenges through native capabilities or custom scripting. Bring machine-learning-based approaches into the flow to lift productivity and trace complex issues to root causes for resolution with EDA vendor R&D teams. Partner with globally distributed teams and mentor junior engineers as they ramp. Requires hands-on fluency with Cadence Genus, Innovus, Tempus, Quantus, Voltus, Pegasus, and Conformal, plus Tcl/Python/Perl scripting. 5+ years in digital implementation flow on advanced nodes.
Required Qualifications
- BE / BTech / ME / MS / MTech in Electrical or Electronics Engineering (or a related field)
- 5+ years in the digital implementation flow on advanced process nodes
- Deep expertise in one or more areas—synthesis, place-and-route, static timing analysis (STA), or EM/IR
- Hands-on fluency with the digital implementation toolchain
- Cadence Genus for RTL synthesis and design-for-test insertion
- Innovus for PnR
- Cadence Tempus for signoff static timing analysis (STA)
- Quantus for parasitic extraction (RC/RCc)
- Voltus / Voltus-Fi for power, EM, and IR-drop signoff
- Pegasus (or Siemens Calibre) for physical verification — DRC, LVS, and ERC
- Cadence Conformal for logic equivalence checking (LEC)
- Scripting in Tcl, Python, or Perl for flow automation and custom utilities
Desired Qualifications
- Familiarity with the equivalent Synopsys flow (Design Compiler / Fusion Compiler, IC Compiler II, PrimeTime, StarRC, Formality)
- Experience implementing high-speed wireline / SerDes-based blocks or SoCs
- Familiarity with low-power (UPF) methodology, DFT, and full physical signoff flows
- Hands-on with multiple tape-outs across advanced CMOS / FinFET nodes
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