ASIC Physical Design Engineer - 7 to 10 years - Pune
On-sitePune, Maharashtra, India
Job Summary
Conduct RTL/netlist-to-GDSII implementation for block-level and full-chip designs in advanced technology nodes. Support digital implementation flows, including hierarchical floor planning, macro placement, I/O planning, and congestion analysis. Perform static timing analysis, analyze timing reports, and implement timing ECOs using industry-standard tools. Run and debug back-end signoff checks, including power integrity, IR/EM analysis, and physical verification. Develop automation scripts using TCL, Python, or Bash for QoR tracking and flow efficiency. Collaborate with RTL, Analog, DFT, Packaging, CAD, and EDA teams to resolve implementation issues and improve design convergence. Assist in defining implementation strategy and physical constraints during concept and planning phases.
Required Qualifications
- Bachelor's degree in Electrical Engineering or related field
- 8-12 years of PD experience in ASIC/SoC physical design and implementation
- Hands-on experience with full physical design flow including floor planning, power planning, place and route, clock tree synthesis, extraction, STA, ECOs, and physical signoff
- Experience with industry‐standard synthesis tools such as Cadence Genus or equivalent
- Place and Route tools like Cadence Innovus
- Static Timing Analysis (STA) tools like Cadence Tempus and/or Synopsys PrimeTime
- Back‐End Reliability & Power Integrity flows using tools such as Cadence Voltus or Ansys RedHawk
- experience with industry‐standard physical verification tools such as Siemens Calibre and/or Cadence Pegasus
- Strong scripting skills in TCL, Python, or Perl for automation and flow development
- Familiarity with ASIC/SoC design flow, DFT concepts, and Linux-based development environments
- Minimum Qualifications Bachelor's or Master's in Electrical Engineering or equivalent field
- 3+ years of PD experience in ASIC/SoC physical design and implementation in advanced CMOS tech nodes
- Proven hands-on experience with the full physical design flow at block and/or chip level PD
- Good understanding of various EDA tools and sign-off criteria
- Must be a team player and be able to collaborate effectively
- Strong analytical, problem-solving, debugging, teamwork skills
Desired Qualifications
- Master's preferred
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