ASIC Packaging Signal/Power Integrity Hardware Engineering Technical Lead (Remote)
$183,800–$263,600 year
RemoteSan Jose, California, United States or Dallas, Texas, United States
San Jose, California, United States or Dallas, Texas, United StatesRemoteFull Time$183,800–$263,600 yearSenior LevelBachelors DegreeEnterprise
Full TimeSenior LevelBachelors DegreeEnterprise
Job Summary
ASIC Packaging Signal/Power Integrity Technical Lead (Remote) — Lead design, verification, and packaging for high-speed ASICs; develop rules for ultra-high-speed signaling; analyze substrate SI/PI and collaborate with layout; create packaging for high-volume production; mentor multi-disciplinary teams; Strong background in 56G PAM4 SerDes, interposers, 2.5D/CoWoS/EMIB, SI/PI tools, and relevant EDA flows; open to remote work within the United States; San Jose, RTP, Acton, Dallas, Tempe, Cary, Carlsbad, and Colorado Springs locations.
Required Qualifications
- Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience
- Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience
- PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience
- High-Speed Architecture & Theory: Expertise in high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis, applied to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
- SI/PI Simulation Proficiency: Experience with pre- and post-layout signal and power integrity (SI/PI) simulations using Cadence Sigrity, Ansys HFSS, Keysight ADS
- Layout Review & Physical Validation: Experience with layout reviews and physical design validation using Cadence APD and Ansys EM flows
- Circuit Analysis: Working knowledge of SPICE for circuit-level analysis, signal modeling, and performance validation
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