ASIC Packaging Signal/Power Integrity Engineer (Hybrid)
$152,500–$219,200 year
HybridSan Jose, California, United States
Job Summary
Develop, document, and implement design rules for ultra-high-speed signaling, ensuring power, performance, and area goals are met for products. Analyze substrate signal integrity (SI) and power integrity (PI), providing feedback and collaborating with the layout team to develop optimal solutions across interposer, substrate, and PCB. Design, document, and develop ASIC packages for high-volume, high-quality release, including post-layout extraction and reporting. Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity and to resolve complex technical issues using advanced technology design rules. Proficiency with pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS; experience with Cadence APD and Ansys EM flows for physical validation. Knowledge of 56G PAM4 SerDes architectures, high-speed memory interfaces (HBM), and 2.5D packaging (CoWoS/EMIB) is preferred.
Required Qualifications
- Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience
- Master's degree in Electrical Engineering and 2+ years of relevant signal and power integrity experience
- PhD in Electrical Engineering and 0+ years of related experience
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