ASIC Front-end Verification Engineer

Front-end Verification Engineer for ASICs using SystemVerilog and UVM. Architect and develop block-level verification environments for sub-systems and full-chip, verify large ASIC blocks, use front-end simulators (VCS/NC), develop verification suites/tests, perform coverage analysis (functional and code), sign off for tape-out, and collaborate with logic designers and software bring-up. Proficiency with SystemVerilog, constrained-random verification, and scripting in Perl/Python/shell is desired; experience with Ethernet/networking protocols is a plus; MSEE or BSEE required.