ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)
On-site · Pune, Maharashtra, India
Job Summary
Lead design verification for high-speed optical transceivers in Cisco’s Client Optics Group, developing UVM-based testbenches, functional coverage, and constrained-random/directd test strategies. Perform block-level and full-chip verification with IPs such as ODSP, D2D IP, SerDes XSR, and SerDes PAM4 drivers/TIA, verify CPU sub-systems, and participate in ATE test planning and release-to-production activities. Requires strong proficiency in SystemVerilog, Python, C, and UVM, plus experience with RTL design, DFT principles, and collaboration within Silicon Photonics teams in Pune, India.
Required Qualifications
- Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
- 12-16 years of functional verification experience
- Strong skills in SystemVerilog, Python, C and UVM methodology
- Familiarity with CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
- Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow
- Excellent organizational, teamwork, and communication skills
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