ASIC DFT Engineer

Job Summary

Required Qualifications

• Bachelors and 12+ years of related experience
• Masters degree and 10+ years of related experience

Desired Qualifications

• Strong DFT background (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
• Scan Insertion and scan compression background (DFT Compiler, Mentor TestKompress, etc.)
• Logic BIST design and debug experience
• Well-versed in ATPG vector generation, simulation, and debugging (TetraMax, Fastscan)
• Experience in Verilog coding, testbench generation & simulation
• Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
• Boundary scan Verification and test vector generation
• Good knowledge in IEEE1149.1 and IEEE1149.6
• Basic knowledge Test-STA and constraints
• Strong background on IEE1687, IJTAG, ICL and PDL
• Ability to work in a multi-disciplined, cross-department environment
• Solid knowledge in analog and digital circuit design, and device physics fundamentals
• Understanding of Si processing, logical and physical synthesis, and transistor reliability principles
• Excellent problem solving, debug, root cause analysis and communication skills
• Strong understanding of statistical process control and data analysis techniques
• Project management capabilities to track and prioritize competing deliverables
• Experience working on ATE is a plus
• Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug is a plus
• Experience working on Tessent SSN is a plus