ASIC DFT Engineer - 7 to 10 yrs
On-site · Bengaluru, Karnataka, India or Hyderabad, Telangana, India
Job Summary
ASIC DFT Engineer responsible for implementing hardware design-for-test features supporting ATE, in-system test, debug, and diagnostics; develop innovative DFT IP in collaboration with multi-functional teams and enable full-chip integration of test logic in RTL; collaborate with design/verification and PD teams to validate testability across implementation and post-silicon flows; 7-10 years of relevant experience with strong knowledge of JTAG, ATPG, Boundary Scan, and DFT/EDA tools (TestMax, Tetramax, Tessent); scripting in Tcl, Python/Perl; post-silicon validation expertise; role located in India (Bangalore or Hyderabad) with on-site expectations.
Required Qualifications
- Bachelor's or Master’s Degree in Electrical or Computer Engineering
- 7-10 years of related work experience in ASIC DFT/Hardware Engineering
- Knowledge of JTAG protocols, Scan insertion and ATPG, Boundary Scan
- Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent
- Experience with Gate level simulation and VCS or other simulators
- Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687
- Scripting skills: Tcl, Python/Perl
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.