ASIC DFT Engineer - 4 to 8 yrs

ASIC DFT Engineer responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Develop innovative DFT IP in collaboration with multi-functional teams and drive full chip design integration with testability features coordinated in RTL. Collaborate with design/verification and PD teams to enable integration and validation of test logic across implementation and post-silicon validation flows. Requires 4-8 years of related experience; Bachelor's or Master's in Electrical or Computer Engineering. Skills include JTAG, ATPG, BScan, TestMax/Tetramax/Tessent, gate-level simulation, VCS, and scripting in Tcl/Python/Perl. Preferred: Post-silicon validation using DFT patterns; Test Static Timing Analysis. Location: Bangalore, India and Hyderabad, India (ON_SITE).